FPGA and Digital Engineer - R&D 2 (7119U) 18958
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The Space Sciences Laboratory (SSL) is the UC system's premier space sciences research facility and one of the preeminent university laboratories in the country for space research. SSL's primary goals of fostering outstanding research in space-related sciences and providing education for the next generation of space scientists. Research at SSL is led by Berkeley faculty and SSL Senior Fellows, and focuses on experiments and observations carried out in space, but also includes research with the potential of leading to future space experiments, and the theoretical research that is tied into the experimental and observational programs. Since its inception in 1959, SSL has participated in over 50 NASA space science missions, including the Apollo, Mars, and Explorer programs, as well as many international space missions.
Application Review Date
The First Review Date for this job is: 6/7/2021
Uses professional engineering concepts to perform moderately complex engineering assignments in the digital electrical engineering specialty and in FPGA design. Works in a specialized engineering phase of a major training and/or research effort. Works on assignments of moderate scope where analysis of situations or data requires a review of a variety of factors. Is responsible for the design, build and test of digital circuitry and interfacing to sensors and analog electronics. Comprehensive FPGA design skills used to design, program and test FPGAs for NASA space flight missions.
- Under general supervision designs digital electrical circuits and performs electrical tests to verify board designs; prepares formal test reports; provide written test procedures to support overall system requirement verification and traceability.
- Under general supervision, designs and prepares FPGA designs and specifications of moderate complexity for NASA funded space research projects.
- Tests electrical boards, and gathers and analyzes data; prepares formal engineering reports, drawings and status reports from those tests.
- A demonstrated knowledge of FPGA design of moderately complicated systems e.g. embedded processors, data processing algorithms and interfacing with other ICs.
- Proficiency with the use of laboratory test equipment, such as multimeters, oscilloscopes, signal generators, and test programming.
- Organizational abilities and decision-making to prioritize work assignments.
- Effective written and verbal communication skills.
- Ability to work in a collaborative manner, to assist in identifying any challenges or barriers.
- Proficiency in FPGA design tools.
- Proficiency with schematic capture and board layout tools.
- Bachelors degree in electrical or electronic engineering or physics with work experience involving FPGA design and testing and digital electrical engineering and / or equivalent experience / training.
Salary & Benefits
Salary commensurate with experience. For information on the comprehensive benefits package offered by the University visit:
How to Apply
Please submit your cover letter and resume as a single attachment when applying.
Conviction History Background
This is a designated position requiring fingerprinting and a background check due to the nature of the job responsibilities. Berkeley does hire people with conviction histories and reviews information received in the context of the job responsibilities. The University reserves the right to make employment contingent upon successful completion of the background check.
Equal Employment Opportunity
The University of California is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status. For more information about your rights as an applicant see:
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To apply, visit https://careerspub.universityofcalifornia.edu/psp/ucb/EMPLOYEE/HRMS/c/HRS_HRAM.HRS_APP_SCHJOB.GBL?Page=HRS_APP_JBPST&Action=U&FOCUS=Applicant&SiteId=21&JobOpeningId=18958&PostingSeq=1