ACCESS is a multi-disciplinary center for advancing IC design and design automation technologies to enable novel data-centric computing paradigms supporting a wide range of AI applications. The research agenda in ACCESS is organized into four research programs, addressing four key technical areas, including 1) Enabling Technology for Emerging Computer Systems, 2) Architecture and Heterogeneous System Integration, 3) AI-Assisted EDA for AI Hardware, and 4) Hardware-Accelerated AI Applications.
ACCESS is seeking high caliber appointees for multiple full-time positions of Research Assistant of our four research programs through the scheme of Research Talent Hub (RTH) of Innovation Technology Commissioner.
The Research Assistants are expected to be involved in the development of one or multiple research programs and projects in the Center. He/she will conduct research and development tasks that are assigned by the Principal and/or Senior Researchers. He/she is required to station and work at the Hong Kong Science Park, with occasional business travels to HKUST Clear Water Bay Campus and other Partner Universities of the Center when needed.
Applicants should have a master degree (MSc or MPhil) preferably in electronics, electrical or computer engineering, computer science, or equivalent, with proven experience in integrated circuit design, design automation or broadly microelectronics and specialized in at least one or more of the technical areas of our four research programs. He/ She must be legally permitted to work in Hong Kong; and in possession of a master degree of a STEM (i.e. Science, Technology, Engineering and Mathematics)-related discipline awarded by a local university, or jointly awarded by a local university together with a non-local university. Specifically, R&D as well as hands-on implementation experiences in the following area(s) with relevance to the design of AI accelerators are preferred (but not limited to):
- ASIC design, FPGA prototyping, AI algorithm design;
- Strong programming skills of at least one of the following languages: Verilog/VHDL, System Verilog, Python, C/C++, Matlab;
- R&D experiences of using Cadence and Synopsys EDA tools or machine learning frameworks such as Caffe, Tensorflow and PyTorch.
The ideal candidate should have strong R&D motivation and sense of responsibility, ability to multi-task and work independently, and a good command of written and spoken English.
Terms of Appointment
Starting salary will be commensurate with qualifications and experience. Fringe benefits including annual leave, medical and dental benefits will be provided. (Duration: 1 year, renewable)
ACCESS is an equal opportunity employer and welcomes applications from all qualified candidates.
For applications/nominations, please apply with a full curriculum vitae indicating their current and expected salaries. Review of applications will begin shortly and continue until the positions are filled. Only shortlisted candidates will be notified.
(Information provided by applications will be used for recruitment and other employment-related purposes.)