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School of Electrical and Electronic Engineering is one of the founding Schools of the Nanyang Technological University. Built on a culture of excellence, the School is renowned for its high academic standards and research.  With over 3,000 undergraduates students and 1,000 graduate students it is one of the largest EEE schools in the world and ranks 10th in the field of Electrical & Electronic Engineering in the 2024 QS World University Rankings by Subjects.

Today, the School has become one of the world’s largest engineering schools that nurtures competent engineers and researchers. Each year, the School graduates over a thousand students who are ready to take on great ambitions and challenges.

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We are looking for a highly skilled Research Associate with experience in RISC-V architecture. The successful candidate will be responsible for adding a Hardware AES and ASCON Accelerator to the RISC-V CVA6 core. This role requires deep knowledge of hardware design, cryptographic algorithms, and the RISC-V instruction set architecture (ISA). You will work closely with the AES and ASCON designers in our team to ensure seamless integration and optimal performance of the cryptographic accelerators.

Key Responsibilities:

Design and Implementation:

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  Integrate a Hardware AES Accelerator and ASCON Lightweight Cryptography Accelerator into the RISC-V CVA6 (Ariane) core.

  
  


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  Implement memory-mapped interfaces or custom instructions for the accelerators to interface with the CVA6 core.

  
  


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  Collaborate on the integration of the accelerators into the core's execution pipeline.

  
  

RISC-V ISA Extension:

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  Define and implement custom RISC-V instructions to utilize the AES and ASCON hardware accelerators, if needed.

  
  


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  Modify the RISC-V CVA6 decode and execution stages to handle the new cryptographic instructions.

  
  


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  Work out the toolchain to ensure assembler, compiler, and simulation support for the custom instructions.

  
  

Verification and Testing:

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  Conduct simulations to evaluate the performance, latency, and throughput of the accelerators within the CVA6 pipeline.

  
  


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  Work closely with the AES and ASCON accelerator design team to ensure proper testing and debugging of the hardware integration.

  
  

Job Requirements:

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  Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

  
  


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  Proven experience with RISC-V architecture, especially with custom instruction extensions and pipeline modifications.

  
  


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  Proficiency in HDL languages (Verilog, VHDL, or SystemVerilog) and RTL design.

  
  


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  Proficiency in toolchain modification, including the ability to extend assemblers and compilers (GCC, LLVM) for custom hardware instructions.

  
  


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  Proficiency of FPGA development tools such as Vivado, Quartus, or similar for prototyping.

  
  

Preferred Additional Skills:

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  Strong understanding of ASIC/FPGA design flows, including synthesis, place and route, and timing closure.

  
  


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  Experience in cryptography and implementing cryptographic algorithms in hardware (AES, ASCON, etc.).

  
  

We regret to inform that only shortlisted candidates will be notified.