School of Electrical and Electronic Engineering is one of the founding Schools of the Nanyang Technological University. Built on a culture of excellence, the School is renowned for its high academic standards and research. With over 3,000 undergraduates students and 2,000 graduate students it is one of the largest EEE schools in the world and ranks 4th in the field of Electrical & Electronic Engineering in the 2025 QS World University Rankings by Subjects.
Today, the School has become one of the world’s largest engineering schools that nurtures competent engineers and researchers. Each year, the School graduates over a thousand students who are ready to take on great ambitions and challenges.
For more details, please view: https://www.ntu.edu.sg/eee
We are looking for a Research Fellow to focus on secure and open-source processor architectures. The incumbent will undertake advanced research on the design, implementation, and integration of cryptographic hardware accelerators within the RISC-V CVA6 (Ariane) core.
The role is structured in two research phases, covering lightweight cryptography (ASCON) and Post-Quantum Cryptography (PQC), and will contribute to high-impact scholarly publications and open-source research outputs.
Key Responsibilities:
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Conduct independent and collaborative research on hardware-based cryptographic acceleration for RISC-V processors.
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Design and integrate a hardware ASCON accelerator within the RISC-V CVA6 core.
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Investigate and implement RISC-V ISA extensions or custom instructions to support cryptographic operations.
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Execute the full ASIC design flow using open-source EDA tools, particularly OpenLane, including RTL design, verification, synthesis, place-and-route, and PPA analysis.
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Research, design, and implement Post-Quantum Cryptographic (PQC) hardware architectures and integrate them into RISC-V systems.
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Evaluate system-level performance, security, and efficiency of cryptographic accelerators.
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Publish research findings in high-quality peer-reviewed journals and conferences.
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Collaborate closely with academic staff, IC designers, and postgraduate researchers.
Job Requirements:
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A completed PhD in Electrical Engineering, Computer Engineering, Computer Science, or a closely related discipline.
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Strong research expertise in RISC-V architecture and processor microarchitecture.
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Proven experience in digital hardware design using Verilog/SystemVerilog or equivalent HDLs.
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Sound knowledge of cryptographic algorithms and secure hardware design principles.
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Experience with ASIC design methodologies and open-source IC design tools, particularly OpenLane.
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Evidence of the ability to conduct independent, high-quality research and disseminate results through publications.
It would be good to possess:
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Prior experience with the CVA6 (Ariane) RISC-V core.
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Research background in ASCON, lightweight cryptography, or hardware security.
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Experience with Post-Quantum Cryptography (PQC) implementations.
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Knowledge of side-channel attack mitigation techniques.
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A strong publication record in relevant international conferences or journals.
We regret to inform that only shortlisted candidates will be notified.
