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Research Opportunity

Digital Electronics, Microprocessors, Heterogeneous Systems

Work description

• Implement the behavior of a RISC-V processor using C/C++;


• Check the feasibility of using the developed code as a RISC-V simulator;


• Check the feasibility of using the developed code for hardware implementation of a RISC-V processor, using HLS tools;


• Compare the implementation with state-of-the-art RISC-V simulators or cores;


• Optionally, add to the implementation the ability to specify extensions to the base instruction set

Academic Qualifications

Enrolment in Licenciatura or MSc in Electronics Engineering, or similar

Minimum profile required

• Programming experience in C/C++;


• Experience with FPGAs and/or hardware accelerators;

Preference factors

• High-Level-Synthesis experience;


• RISC-V experience

Application Period

Since 18 Apr 2024 to 03 May 2024

Maintenance stipend: € 601,12, according to the table of monthly maintenance stipend for FCT grants , paid via bank transfer. Grant holders may be awarded potential supplements, according to a quarterly evaluation process (Articles 19, 21 and 22 of the Regulations for Grants of INESC TEC and Annex II), up to a maximum limit of 50% of the monthly maintenance stipend.

Centre

Telecommunications and Multimedia

Scientific Advisor

Nuno Miguel Paulino

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